// Cause Register
// The cause register is used describe the cause of an exception in exception handling code
// the register lives on CP0 but is described here because it is used soley during exceptions.
// Cause Layoyt:
//   31   30  29   28 27    26  25  24 23   22  21  16 15   10 9     8 7  6        2 1 0
// | BD | TI |  CE  | DC | PCI |  0  | IV | WP |  0  | IP7-2 | IP1-0 | 0 | ExcCode | 0 |
//                                                   | RIPL  |

#define CR_BRANCH_DELAY		(1 << 31)	// Exception occurred in branch delay slot, EPC points to branch
#define CR_TIMER_INT		(1 << 30)	// Internal timer caused the interrupt
#define CR_CP_ERROR			0x30000000	// If SR(CUx) == 0 caused an exception Cause(CE) == x
#define CR_DISABLE_COUNT	(1 << 27)	// Disable the count register (WRITE)
#define CR_PERF_OVFLOW		(1 << 26)	// A performance counter overflowed causing the interrupt
#define CR_INT_VECTOR		(1 << 23)	// Enable custom vectors for interrupts (WRITE)
#define CR_WATCHPOINT		(1 << 22)	// Indicates a watchpoint int is in the queue
										// this bit can also be set to affect interupt handlers
#define CR_PENDING			0xFF00		// Bits in this field indicate pending interrupts
#define CR_EXC_CODE			0x7C		// Indicates the type of exception

// ExcCode values:
enum {
	kCRCode_Int				= 0,	// Interrupt
	kCRCode_Mod				= 1,	// Store to r/o page
	kCRCode_TLBL			= 2,	// TLB miss
	kCRCode_TLBS			= 3,	// TLB miss during an exception
	kCRCode_AdEL			= 4,	// Address error on load (either a miss aligned read or an
									// attempt by user code to read outside of kuseg)
	kCRCode_AdES			= 5,	// Same as AdEL but for store rather than load
	kCRCode_IBE				= 6,	// Bus error on data fetch
	kCRCode_DBE				= 7,	// Bus error on data store (indirect through cache)
	kCRCode_Syscall			= 8,	// syscall instruction executed
	kCRCode_Bp				= 9,	// break instruction executed
	kCRCode_RI				= 10,	// instruction not legal or not recognized
	kCRCode_CpU				= 11,	// Attempt to run a coprocessor instuction on a disabled CP
	kCRCode_Ov				= 12,	// Overflow from trapping form of arithmetic
	kCRCode_TRAP			= 13,	// Condition met on conditional trap instruction
	kCRCode_FPE				= 15,	// Floating point exception
	// 16-17 are avail for impl
	kCRCode_C2E				= 18,	// Exception from CP2
	kCRCode_MDMX			= 22,	// Tried to run an MDMX instruction but SR(MX) wasn't set
									// perhaps CPU doesn't do MDMX
	kCRCode_Watch			= 23,	// Physical address of a load/store matched enabled value in
									// WatchLo/WatchHi registers
	kCRCode_MCheck			= 24,	// CPU detected disastrous error in CPU state/functionality
	kCRCode_Thread			= 25,	// Thread related exception
	kCRCode_DSP				= 26,	// Attempt to run DSP ASE instruction but CPU doesn't support
									// DSP or SR(MMX) isn't set to enable it
	kCRCode_CacheErr		= 30,	// Parity ECC error, not normally visible anywhere
};

